Icarus Verilog Mini How To

For my Free Telephony Hardware project I need to program a small Xilinx CPLD to handle some SPI bus decoding.

I have been using the gEDA tools for schematic entry and PCB design. gEDA also includes Icarus Verilog so I decided to check it out.

Verilog is a hardware description language. Instead of drawing schematic circuit diagrams you use source code to describe digital logic. Like this:
module d_ff( d, clk, q, q_bar);
input d, clk;
output q, q_bar;
reg q;
reg q_bar;

always @ (posedge clk)
q <= d;
q_bar <= !d;

This is the Verilog source for d_ff.vl, a D flip-flop. Here is a “test bench” (d_ff_tb.vl) to drive the D flip-flop:
module d_ff_tb;

reg clock, reset, d;
wire q, q_bar;

initial begin
$dumpfile ("d_ff_tb.vcd");
$dumpvars (1, d_ff_tb);
$monitor ("clock=%b, d=%b, q=%b, q_bar=%b", clock, d, q, q_bar);
clock = 0;
d = 1;
#10 d = 0;
#20 $finish;

always begin
#5 clock = !clock;

d_ff d0(
.d (d),
.clk (clock),
.q (q),
.q_bar (q_bar)


You can see the instance of the d_ff at the bottom, and the notation used to tie its “terminals” to nets in the test bench. You compile and run like this:
$ iverilog -o d_ff_tb d_ff_tb.vl d_ff.vl
$ vvp d_ff_tb
VCD info: dumpfile d_ff_tb.vcd opened for output.
clock=0, d=1, q=x, q_bar=x
clock=1, d=1, q=1, q_bar=0
clock=0, d=0, q=1, q_bar=0
clock=1, d=0, q=0, q_bar=1
clock=0, d=0, q=0, q_bar=1
clock=1, d=0, q=0, q_bar=1

You can see the flip-flop being put through its paces. First we set d=1, then on the next rising edge of the clock you can see q and q_bar change. Then we try d=0 for a few clock cycles. There is also a companion program called GTKWave that allows you to plot waveforms:

BTW I gotta say I just love the splash screen from GTKwave! I always knew engineering was as cool as surfing:

I have done a little VHDL coding (VHDL is a cousin of Verilog) using Windows GUI based tools (using a Xilinx IDE and ModelSim) and actually found it quite painful to get started and run simple simulations. So I was pleasantly surprised with how easy it was to use Icarus to develop and test simple logic designs.

Even though I had never used Verilog before it only took me about 3 hours of research on the web to get the simple simulation above written and running. This is very cool, I actually found this much easier than my first VHDL experience on a Windows GUI. Thank you very much and kudos to Stephen Williams who wrote Icarus Verilog (and thanks also to the developers of GTKWave).

I think one of the great features of Icarus is that it uses the command line and text files for everything, rather than the typical bloated Windows GUI approach. I am a big fan of the command line & text files, for example in the other gEDA tools like gschem (schematic entry) and PCB (PCB layout) text files are used to store the designs. This makes powerful processing and automation possible like manipulating PCB designs using Perl.

As an aside the Pragmatic Programmer guys have a good article on the benefits of text files here.

I am a raw beginner at Verilog and found the tutorial information on the Asic World site to be very useful. Thanks Deepak Kumar Tala for putting that site together.

10 thoughts on “Icarus Verilog Mini How To”

  1. Thanks for describing your design effort. Please tell me, (all of us), about the cpld you used, and did you use icarus PAL, or another back end that’s part of the usual releases

  2. Hi John,

    The example in the blog above was not actually synthesised, it was just a way of getting started with Verilog.

    However I have since implemented some glue logic for my Free Telephony Project using the same techniques. For this application I used a Xilinx XC9536, which are about $1.60 from Digikey. I used the Xilinx Webpack software (free download) to synthesise and program the CPLD. I have some notes on the actual design I implemented (along with the source and test benches) in the cpld directory of this tar ball:


    – David

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