EMI Testing 101


Electromagnetic Interference (EMI) testing measures the amount of energy your electronic product radiates. If it radiates too much EMI, it might interfere with other products, for example a PC with bad EMI might make it hard to use your radio or cell phone.

EMI is a growing problem, as most devices contains some sort of computer, and the frequencies of clock signals are rising all the time. All those fast signals can potentially create lots of EMI.

EMI tests can be a stressful time in the product development cycle. These tests are usually occur right at the end, when the budget is blown, you are overdue and you need to get that product out the door “or else”. They are expensive (especially for small companies) and are “make or break” – a failure could send you back to the drawing board to redesign the printed circuit board costing months of development time.

My EMI Testing Experience

There are certain standards that you need to meet for EMI. In October 2006 I attempted to obtain US/Australian/European EMI compliance for the following system (the 4fx telephony boards combined with a BF537 STAMP):

The tests were performed by Austest, in their Adelaide Labs. The US standard for EMI is known as FCC-15. The Australian/European standards overlap in most areas so can be performed at the same time.

The idea was to use the STAMP (an off the shelf development board from Analog Devices) plus my 4fx daughter board to get a first pass product “to market” quickly, without the engineering effort required to develop our own Blackfin motherboard. This would be a a good way to get the technology into real world use quickly. We could then follow up with a lower cost/volume manufactured custom motherboard.

Unfortunately, I flunked part of the tests. Below I describe why I flunked and how I traced the problem. I have got to admit that this hurts – these tests cost me around US$3,000 out of my own pocket! However maybe by blogging on it I can share some of the experience I gained and help share some of the value from the tests.

This means that we can’t use the STAMP/4fx combination for a real-world, volume manufactured product, although it’s OK for “test and evaluation” (the EMI standards generally have exemptions for development work).

The good news is the telephony daughter board looks good from an EMI point of view – it was the STAMP board that was radiating too strongly to meet the requirements of FCC-15. So with a Blackfin DSP motherboard designed to minimise EMI we should be able to eventually pass the EMI tests OK.

The EMI Test Procedure

The EMI tests are designed to accurately measure radiation from your product, called the Equipment Under Test or EUT. Radiation can come from a variety of sources:

  1. Any cable connected to your device can act as an effective antenna under the right circumstances. For example power cables, Ethernet, and phone cables.
  2. The Printed Circuit Board (PCB) can also radiate directly. High frequency currents can flow around the board, for example from a clock oscillator through the power supply rails. If the loop area of the current is large (say due to the PCB layout), it may radiate EMI.

The FCC-15 tests are divided into two sorts of tests, designed to pick up EMI in different parts of the spectrum:

  1. Conducted tests, where voltages conducted down the cables are sampled.
  2. Radiated tests, where the actual radiation of the EUT is measured using an antenna.

Conducted tests

Conducted tests are used for lower frequencies (150kHz to 30MHz). Low frequency signals have long wavelengths. At these frequencies it’s easier to determine if the EUT is likely to radiate by sampling the voltages on the cables connected to the EUT, rather than say using an antenna. Otherwise you might need very large antennas (like several km long) to be sensitive to radiations at low frequencies. Common problem at these frequencies are switching power supply noise. For example those big lumps in your power supply cables are ferrites that are designed to block power supply noise travelling down the power supply cable.

The conducted tests were performed inside a shielded room. Note the careful arrangement of the EUT, wires were connected to all ports to simulate real world operation. Any little change in this configuration could change the EMI signature.

To sample the signals special boxes are used that are carefully calibrated to sample any EMI signals on the Ethernet/telephone/power cables without affecting normal operation:

The signals detected by these boxes are fed to a spectrum analyser – a device that can measure the EMI energy in various parts of the spectrum and determine if it is above or beneath the required levels.

The levels for the conducted tests were sampled from the power, Ethernet, RS232 serial, FXS and FXO ports and found to meet the requirements. All well and good, so on to the radiated tests.

Radiated Tests

For higher frequencies (30MHz to 1.5GHz in this case), an antenna is used to directly sense EMI from the EUT. The test lab I used have an outdoor test site:

Outdoor test sites tend to be in relatively remote locations, away from any ambient sources of radio waves that might interfere with the tests. You can see that this site is in a valley, with only a few houses in sight. The sites are carefully calibrated each time they are used to make sure there are no new sources of “ambients”.

The EUT is placed on a rotating table, so its EMI radiation can be measured at different angles:

A very special (and very expensive) antenna is used to sense the EMI radiation. This is carefully calibrated and has a known response across the frequencies of interest:

Below is an example of the typical test results. This graph measures the level of EMI energy between 30MHz and 1500MHz. Click on the image to get a larger, more legible version.

The green line shows the background (or ambient) radio signals at the site, the black line shows the combination of ambient plus the EUT. The red and blue lines show the permissible limits.

During the tests the antenna is moved up and down, and the EUT table rotated to maximise the signals from the EUT at various frequencies. The EMI signature tends to vary a lot with orientation and antenna height.

It was here that we hit some problems – the EUT was radiating a very strong signal at 300MHz – far exceeding the level allowable by the standard. The 300MHz signal was about as strong as a small radio transmitter (for example like one used to open your car doors)!

By a process of elimination we tracked the problem down to STAMP board itself. When all the cables (except power) and the telephony daughter boards were removed the STAMP sat there radiating approximately the same signal at 300MHz.

After a few hours of attempting to reduce the EMI level at 300MHz (for example shielded boxes, and metal plates under the STAMP board) we called it a day – the signal was just too strong to be easily fixed.

I guess the good news was that my telephony boards were fairly clean – telephony boards often have problems with radiation from phone cables (they make good antennas for EMI). However adding and removing the daughter boards and phone cables didn’t have much effect on the EMI levels.

Somewhat (OK very) disappointed, I retired to home base to think about the problem and do some tests.

Now I should emphasise that the BF537 STAMP board was not designed for EMI compliance, rather it was optimised for development purposes. These two requirements are at odds, for example on the STAMP all of the high speed address/data bus nets are routed to headers, which means lots of extra high speed nets on the board, all potential EMI radiators. In a commercial, FCC-15 compliant design, the number and length of high speed nets would be minimised. I was just hoping that the STAMP would be FCC-15 compliant and therefore suitable for early deployment of my telephony systems. So I took a chance and messed up. My mistake.

However I learnt a lot and had fun tracing the source of the EMI, as described below.

The Elusive EMI Bug Hunt

To track the problem I built a little sniffer probe: two turns of wire connected to 50 ohm coax. I viewed the signal from the sniffer using a 500MHz scope with the input set for 50 ohm termination. One handy feature of my scope was a FFT function – this let me see the 300 MHz signal on a frequency scale. I could also see the signal on the regular time domain display when the sniffer probe was close to the STAMP.

When placed near the STAMP PCB a very clear 300MHz signal can be seen. The level of the signal varies as the probe is moved over different parts of the board.

Here is a picture of the sniffer probe in action. It is like a poor antenna, that picks up EMI from just a few cm away – useful for localising the source of the EMI on the PCB.

Here are the initial results:

  1. I found that the 300MHz noise was all over the ground plane, but is not present in the power cable. This suggests that the noise is not being radiated by the power cable.
  2. I found peaks in the signal level over the SDRAM chips. This is expected, as there is a 100MHz bus connecting the SDRAM chips to the CPU, which means lots of digital noise.
  3. Curiously, I found another big peak over the “Blackfin” graphic (see photo above). This peak was not expected, as there were no parts loaded on this part of the PCB (on the upper or lower side).

Now 300MHz is the 3rd harmonic of the 100MHz bus frequency. Digital signals are square waves which are made up of odd-harmonics of the square wave frequency, so from a 100MHz bus we would expect to see energy at 100MHz, 300MHz, 500MHz, etc.

I guessed that the 300MHz signal was a harmonic of the 100MHz bus that for some reason was radiating effectively from the PCB. To test this theory I changed the bus frequency to 125MHz, and saw the strong signal at 300MHz shift up to 375MHz. So it looks like the source of the EMI is the bus.

Now to radiate EMI you need a signal source (the bus in this case) and an effective antenna (for example a cable around one quarter of the wavelength or a current loop of similar size).

I suspect the PCB has a resonance at around 300MHz. This would explain why the signal is so strong at 300MHz but the fundamental (100MHz) and 5th harmonic (500MHz) are not visible on the scope.

At 300MHz, a good 1/4 wave antenna would be 25cm long – close to the length of the board. There could be AC currents travelling over tracks of that length of the PCB board.

Splits in PCB Power Plane

Fortunately the STAMP designs are all open. I therefore inspected the BF537 STAMP Gerber files, which are available from the Blackfin site. Gerber files are the graphics files that define the Printed Circuit Board (PCB) layout. They are the files you send to the PCB house to get your boards made. The BF537 STAMP board is an 8 layer design.

There is a very nice Linux Gerber viewer program called gerbv that comes with the gEDA tools that I have used to design the 4fx hardware. To view the Gerber files I unzipped the STAMP Gerbers then ran gerbv:
$gerbv *.pho&

I took a look at the PCB in the area of the Blackfin logo:

The image above has the layer 0 (a signal layer) and layer 1 (VCC power plane) displayed. Layer 0 has some wiring for high speed signals. Layer 1 is the VCC plane and is split into areas for each VCC rail (5V, 3V3, 1V2 etc).

Now remember that my sniffer found a peak over the Blackfin logo – this area is the rectangular box in the image above. Curiously, this area corresponds to a split in layer 1, the VCC plane.

High speed digital signals like to take the path of least impedance, i.e. the most direct path (Note: see comment below by Icarus75 on this). They tend to flow out of a pin, along a net, then back through the ground or power plane to the ground pin of the chip generating the signal.

A split in power or ground plane causes the signal to take a longer path (it must flow around the split), causing the total loop area to increase. Signals flowing through large loop areas make good antennas for EMI.

If layer 1 is placed directly under Layer 0 it will not be doing a good job as an signal return path – the splits will cause signals to take big detours, with large loop areas, and generate lots of EMI (plus possibly other high speed digital issues).

To minimise loop area (and hence EMI) you really want a continuous plane (VCC or GND) under any high speed nets.

So my theory is that the EMI is being caused by having a split power plane directly beneath a high speed signal layer, i.e. the problem may be the PCB layout, or more correctly the ordering of the layers in the PCB. This theory is supported by the high level of the problem 300MHz signal found over a split in the VCC plane.

Next Steps

The next step is to design a new DSP motherboard that is FCC-15 compliant. As a first step I have been working with a team of open developers on the BlackfinOne project. This is Blackfin DSP motherboard, designed using the gEDA open CAD tools by a community of developers. This design has been customised a little for telephony work and some steps have been taken at the design stage to minimise EMI. Several people in the BlackfinOne community now have this design up and running.

When I have loaded my BlackfinOne, I will do some preliminary in-house testing of the design before determining if the board will be submitted for FCC-15 testing. It is possible to construct some test jigs to do preliminary EMI testing outside of the EMI labs. Although uncalibrated, it should be possible to determine if there are any serious problems. More on this in another post!


Thanks to Paul Kay at Austest for patiently explaining to me the issues involved with EMI. Despite the poor results, he made the two days we spent testing enjoyable and a fascinating learning experience!
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12 thoughts on “EMI Testing 101”

  1. Great work as always, thanks for all your hard work.

    Hopefully the BlackfinOne will have no EMI issues, can’t wait for it to be available to try it out.

    I work for a small company that does mainly telephony work, this could be a great way to replace panasonic pbx’s, there is a market for more robust and feature rich equipment, but not that much of a buying power here in guatemala, this will hopefully help us bring such technology to more people.

    On the low-en we haven’t ben able to compete at all with the panasonics they cost from 100-300$, sure they dont deliver everything that an asterisk box could, but some people dont need everything either.

    BTW, do you think this hardware is capable of running E1/T1’s?

  2. Thanks Chema. Yes I do think the Blackfin is capable of running a T1/E1. It depends on how much echo cancellation is required.

    What sort of low end PBX can u buy locally for $100-$300? Is that new, does it include handsets?

    – David

  3. Very basic panasonics can be had for 200-300, 2 external lines and 4-8 extensions, it does not include handsets. I’m not sure if they’re new or not but that’s what people go for on a tight budget even if it doesn’t do everything they would like to.

    They havent been introduced to asterisk, and frankly just considering the costs of the digium fxo/fxs cards it’s already out of their budget without a PC and profit for the one selling them the solution.

    And to consider that with VoIP they only really need 2 fxo ports for the external lines, and VoIP for the phones and international calls. the cost for that locally is like 300$ for a very cheap lowend machine, 300$ for a digium card with 2 fxo after shipping and taxes, for 600$ without any headsets it can do everything one would want out of a PBX, but some people dont want everything but a cheap price.

  4. Thanks for that information, Chema.

    Do you think people in your market would be more likely to use FXS ports/analog phones for the handsets, or would they use IP phones?

    I guess analog phones would be much cheaper. The advantage of IP phones (as you mentioned above) is that the IP-PBX is simpler as you only need FXO ports.

    – David

  5. It really depends on the infrastructure the client has, if he already has a good ethernet network i think he’s more likely to use IP phones, the grandstream are between 37-49$, whereas a fxs card + the cheap analog phones is already above that, it also might be cheaper to use ATA’s instead of fxs cards and hide away the ATA’s to ease transition.

    But if the client doesn’t have a good ethernet network it might be cheaper to go with analog phones instead of cabling and buying switches.

    That’s mainly why we dont offer pre-configured asterisk boxes, which would be cheaper for us to do, but could very well not be what the customer wants.

  6. Well I can make a FXS port for US$20 at present, and probably US$10 if we get the volume up. Would that make FXS/analog phones more of an option?

    A Blackfin * PBX could probably handle 24 ports of FXS if u dont do VOIP on all of them at the same time. All of the CPU load is in the echo cancellation, so if it’s just switching between analog ports the CPU load is trivial.

    This would mean a 24 port analog/IP-PBX for 24 x $20 + $150 = $630. That is the build price, excluding profits. Less in greater volume.

  7. High speed digital signals like to take the path of least resistance, the most direct path. They tend to flow out of a pin, along a net, then back through the ground or power plane to the ground pin of the chip generating the signal.

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  8. Hello David,

    Very nice post about your close-encounters with EMC issues. I am using a similar sniffer probe attached to a spectrum analyzer to search for excessive emissions on the new Fluksometer.

    I do think there is a minor inconsistency in your text:
    “High speed digital signals like to take the path of least impedance, i.e. the most direct path. They tend to flow out of a pin, along a net, then back through the ground or power plane to the ground pin of the chip generating the signal.”

    HF signals will indeed take the path of least impedance. This should not however be confused with ‘the most direct path’, which I interpret as being the shortest path. Given a massive ground (or Vcc) plane as a return path, the return current will, according to Lenz’ law, flow along the path of least inductance (which is at these frequencies >> resistance). So if your signal trace meanders across the board, the return current in the ground plane will as well, hugging as close as possible to the signal trace. The higher the signal frequency, the bigger the hugging effect. See [1] for an experiment showing the effect of different return paths for a 100MHz signal.

    [1] doc.utwente.nl/68420/1/1569229621.pdf


    1. Yes Bart you are right, thanks for pointing out the track-hugging nature of high speed signals. It’s a good image to keep in mind when laying out PCBs.

      I think of the loop area when drawing a track, and focus on keeping the loop area small. I avoid meandering tracks, try to keep them direct. I also think about where the currents flow, as mixing the return currents from different sources (say digital and analog) can cause problems.

      I am thinking about how your model works with a problem track like the ones above that cross a split in the plane. In that case the DC resistance is larger than the inductive reactance – the split is an insulator. So the current will have to take a path around say the border of the plane, a very high inductance path with a large loop area. That’s why I like the term “path of least impedance” – it takes into account resistive and reactive components.

      Also the actual current path is perhaps a probability density function about the minimum impedance path. It’s like there are many impedances in parallel through all possible return paths in the plane.

  9. Like the test setup tried to prove in the paper, the model of HF signals following the path of least inductance is counter-intuitive, but correct. One conclusion is that if you place the analog and digital section of a mixed-signal design in different locations of the PCB and never run an digital track through the analog section or vice-versa, then you can just use one single massive ground plane. Digital and and analog HF signals will cause return currents in the ground plane that flow directly underneath their original signal.

    I guess the error these guys made was to cut the ground plane in the first place while a better partitioning of analog and digital sections, combined with a massive ground plane would have done the job. See also [2] for a more elaborate discussion on why you should (almost) never cut your ground plane.

    As for the probability density function, this will most likely be the case. However, any return current not flowing right underneath its AC signal would be subjected to a force pointing towards the signal track due to Lenz’s law. The higher the frequency, the higher the force. The only way then to get a PDF would be due to an opposing force. I think one opposing force would be the increased thermal agitation of the electrons due to the (slight) heating of the conductor where the current is initially flowing. And in the case of a meandering signal, the slightly higher resistance compared to a straight return track would also be a component. But then again, the higher the frequency, the more insignificant these counter forces become.

    [2] http://www.hottconsultants.com/techtips/split-gnd-plane.html

  10. Hi Bart,

    It’s quite amazing to think about a high frequency current being forced onto a certain path by electro-magnetic forces. Very cool. Although I still like the idea of taking special care to keep high speed nets short and straight, to minimise the total loop area.

    Many digital signals will have frequency components right down to DC. I guess these currents will take all sorts of different paths. For example a DSP system that executes a bunch of software at the sample rate might have a bus that is bursting off and on at audio frequencies.

    I like the partitioning approach in [2], and have used it several times with good results. Their idea of multiple plane partitions for extra ADCs is even cooler, that is a new trick for me.

    Although naming conventions vary – what [2] calls partitioning I have heard described as split planes with a single point ground connection between split planes. I also use this technique with two layer PCBS (with no ground plane) – I think about where the ground currents flow and separate ground nets between sensitive and noisy circuit areas, with just a single point connection.

    But whatever you call it the key point is to avoid any digital currents flowing through analog ground plane sections. An issue with the STAMP design above is digital nets meandering over ground plane splits, as [2] points out this is not a good idea. It causes big inductive loops which are nice antennas. The first figure in [2] shows the right approach.

    I have a mental model of digital ground currents passing thru the ground plane. At high frequencies the ground plane impedance is complex (reactive and resistive components). So via Ohms law currents in the ground plane create time varying voltage drops in the ground system – noise sources. We don’t want these noise sources in series with our analog ground, so it’s a good idea to avoid analog and digital currents in the same ground path.

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