# Simple Low Pass Digital Filter Design

For the \$10 ATA DC-DC converter I need to design a low pass filter so that the discrete time model matches the real world DC-DC converter hardware. Given the time constant (tau), and the sampling rate Fs, I want to work out a value for c in the DC-DC converter discrete time model. In the original post I glossed over the process so here is a more detailed explanation. This post requires some maths and engineering knowledge, more than my normal posts. It also exposes some glaring gaps in my own ability to explain concepts I use every day as an Engineer.

I use simple digital filters quite a lot, e.g. in the Oslec echo canceller I have some high pass filters that are very similar. So if I document the design process here I won’t have to work it out again or go shuffling through my log books. You might find it useful for designing simple digital filters as well.

To make the notation a little bit easier I have used changed the original variable names by making the substitution y(n)=Vbatt(n) and x(n)=pwm(n). First lets re-arrange the discrete time equations:

Now we zap the whole thing with the mysterious Z-transform. This transforms the system into the “Z-domain”. Sounds a bit twilight zone. You know I sometimes feel like I am in the Z-domain before my morning coffee. But it can make discrete time systems easier to analyse, as will become clear.

Without worrying too much about the maths you just change y(n) to Y(z), x(n) to X(z) etc. Any delays in the discrete time model get converted to a power of z. We can then re-arrange to get a transfer function Y(Z)/X(z) which describes the system:

I rendered these equations using Roger’s online equations.

This exposes some gaps in my knowledge. I really would like to be able to explain why we use the Z-transform and exactly how it works. However I slept through that part of University. I was probably thinking about beer and girls just as the crucial points were explained. Or playing pinball in the Sports Centre. When I was younger, it seemed enough to “just know the formula”, so that’s what I have retained. That got me a long way but doesn’t seem enough now.

The roots of the top and bottom line of the transfer function are known as the zeros and poles. In this case there is one pole at z=1-c, drawn as a cross in (a) below.

We can map test signals onto the Z-plane, and use them to work out the gain of the system at any frequency. On the Z-plane, a sinusoidal test signal P maps to a point on the perimeter of the unit circle. The position of P is given by z=exp(jw), where w is the normalised frequency in radians. As w increases, P moves around the unit circle. DC (0Hz) or w=0 maps to the point z=exp(0)=1. The aliasing frequency w=pi maps to z=exp(j*pi)=-1. We can work out the gain of the system at any frequency by taking the numerator k of the transfer function and dividing it by the distance from P to the pole. This gives us a neat way to design the frequency response of the system using geometry.

For our DC-DC converter we know the time constant tau. We want to find c for a given sampling rate Fs. In terms of the Pole-Zero diagram we want to select c to place the pole in the right spot to get a certain frequency response.

Now from analog time constant theory the -3dB cut off frequency Fc in Hz is 1/(2*pi*tau). For a sampled system, Fc in normalised radians is w=2*pi*Fc/Fs. If we substitute Fc=1/(2*pi*tau) we get w=1/(tau*Fs) as the cut off frequency in normalised radians.

(b) is a close up of the Z-plane for small frequencies w. As the frequency increases P moves from w=0 (0 Hz) and the distance between P and the pole starts to increase. At w=0 the distance from the unit circle to the pole is c. So the gain is k/c. At the -3dB cut-off we want the gain to be 3dB down on the gain at w=0, or 3dB less than k/c. So at the -3dB cut off the distance from P to the pole must be 3dB more or sqrt(2)*c.

Now h=sin(w)/1 but for small angles we can use the approximation sin(x)=x (try it on you calculator) so we approximate h=w. We can draw a right angle triangle between the pole to P to z=1. The length of one side is c, the height is h=w=1/(tau*Fs), and the hypotenuse is sqrt(2)*c.

So a bit of Pythagoras gives us c=1/(tau*Fs), which we can plug back into our discrete time model. A surprisingly simple answer which despite this post I still feel I haven’t explained very well!

1. In the \$10 ATA Part 4 post I derived the discrete time DC-DC converter model that was analysed in this post.
2. This post on Fixed Point Scaling has another example of a very similar low pass filter.
3. Oslec source code. I use some high pass filters in Oslec to block DC. They can be analysed in a way very similar to the system above. The Oslec High Pass filters have a zero at w=0 which means they block any DC (steady state) signals. The pole is placed to set the bandwidth of the high pass filter, it helps form a notch around DC. These filters have some messy fixed point scaling which unfortunately obscures their operation.

## 2 thoughts on “Simple Low Pass Digital Filter Design”

1. Nissim says:

Hi Davi
Thanks for the description. I shows you are have very intuitive understanding

thanks for