Over the past couple of years a few people have suggested running Asterisk on an FPGA using an embedded processor core. I must admit I had always assumed that the processor would be too slow to be useful, certainly much slower than a regular embedded processor at the same price.
However my friend Stelios Koroneos and the team at Digital OPSiS have proved me wrong! They have managed to implement Asterisk on a Xilinx Virtex 4 FPGA, running a 300MHz Power PC core. These FPGAs cost about the same as an embedded processor, e.g. around $12 in Qty 1000.
They have the whole system running on a Xilinx development board:
Many clever tricks are possible with a FPGA, for example you can just “compile in” a floating point unit, include all your system glue logic on the same FPGA, or provide hardware acceleration for application specific tasks. In this case, FIR filters used for echo cancellation have been sped up by a factor of 300, using a little custom hardware implemented on the FPGA.
The build process is interesting, you first “build” (synthesise) the actual CPU (!), then build the kernel, applications etc to suit. Booting is also interesting. On power up the first step is to configure the RAM-based FPGA, then like magic it turns into a CPU and the regular boot loader plus Linux boot process can commence. Both the FPGA configuration data and Linux can be stored on a SD card (and presumably be updated by Linux at run time).
This is pretty amazing stuff, and opens up some really interesting possibilities. For example you could include an E1 framer on the FPGA and possibly even the DSP side of analog interfaces. The Bill of Materials BOM can also be reduced by absorbing system functions into the FPGA. Stelios and team are also working on hardware-acceleration for codecs like G729.
CPU cores embedded on an FPGA represents a “third way” to build embedded IP-PBX systems. Earlier designs used a host processor + specialised DSP architecture, later systems (like Asterisk on an x86 or the IP04) use a host-processing approach where a single CPU with DSP capabilities is employed.
I really like the Digital OPSiS guys think – they are digging into the key issues of Asterisk (like the drawbacks of it’s threaded design and bottlenecks like echo cancellation) and coming up with fascinating new ways to optimise the system.
Nice work Digital OPSiS!