Asterisk on a FPGA

Over the past couple of years a few people have suggested running Asterisk on an FPGA using an embedded processor core. I must admit I had always assumed that the processor would be too slow to be useful, certainly much slower than a regular embedded processor at the same price.

However my friend Stelios Koroneos and the team at Digital OPSiS have proved me wrong! They have managed to implement Asterisk on a Xilinx Virtex 4 FPGA, running a 300MHz Power PC core. These FPGAs cost about the same as an embedded processor, e.g. around $12 in Qty 1000.

They have the whole system running on a Xilinx development board:

Many clever tricks are possible with a FPGA, for example you can just “compile in” a floating point unit, include all your system glue logic on the same FPGA, or provide hardware acceleration for application specific tasks. In this case, FIR filters used for echo cancellation have been sped up by a factor of 300, using a little custom hardware implemented on the FPGA.

The build process is interesting, you first “build” (synthesise) the actual CPU (!), then build the kernel, applications etc to suit. Booting is also interesting. On power up the first step is to configure the RAM-based FPGA, then like magic it turns into a CPU and the regular boot loader plus Linux boot process can commence. Both the FPGA configuration data and Linux can be stored on a SD card (and presumably be updated by Linux at run time).

This is pretty amazing stuff, and opens up some really interesting possibilities. For example you could include an E1 framer on the FPGA and possibly even the DSP side of analog interfaces. The Bill of Materials BOM can also be reduced by absorbing system functions into the FPGA. Stelios and team are also working on hardware-acceleration for codecs like G729.

CPU cores embedded on an FPGA represents a “third way” to build embedded IP-PBX systems. Earlier designs used a host processor + specialised DSP architecture, later systems (like Asterisk on an x86 or the IP04) use a host-processing approach where a single CPU with DSP capabilities is employed.

I really like the Digital OPSiS guys think – they are digging into the key issues of Asterisk (like the drawbacks of it’s threaded design and bottlenecks like echo cancellation) and coming up with fascinating new ways to optimise the system.

Nice work Digital OPSiS!

9 comments to Asterisk on a FPGA

  • Most FPGA boards these days include an embedded processor in them (which is not actually part of the gate array). These processors are generally a PPC or ARM based. You can then use the FPGA to speed up various functions as you suggested.

    Another really cool thing about using a FPGA is the interface options you have. It is easy to model most PC interface devices such as SATA, Ethernet, USB in the FPGA.

    I look forward to see more about this.

  • Karim Mardhani

    This is interesting topic but what about the cost? Wouldn’t Xilinix charge for their IP (in this case the processor)? Or is the IP cost is included in the cost of the FPGA chip?

  • Actually, I’ve heard of some people at a German university who did an FPGA port or Speex. Maybe I should check again with them to see whether it’s completed and they’d be willing to release it…

  • Almost all of the IP is provided by Xilinx for “free”. (You actually pay for it when you buy the Embedded Dev software kit. approx 500$)
    This includes the ppc cpu,ethernet,serial and a few more blocks.
    There are other blocks that you need to licence from Xilinx with an one time fee. i.e the fpu is $1000 and similar is the cost if you deside to use a “full blown” uart ip block insted of the uart-lite.
    Even for the IP you need to pay for, you can test it before bying and build a system with it that will work for 8 hours and then that particular ip block will stop to function.

  • There are few boards available for few hundred bucks (much less then 500). You should be able to find it out via either xilinx.com or via http://www.fpgacentral.com/fpga-boards/catalog which has a list of all boards

  • I found some free time during my vecations and have uploaded the Astricon presentation for those who have requested (or want to have a look).
    http://www.digital-opsis.com/downloads/Running_Asterisk_on_FPGA.ppt

  • JC

    I don’t understand how this works on an ML403. How do you connect the FXS/FXO ports (phones and the incoming line)? Is there a custom PCB designed for this purpose?

    Also, noticed that this blog post is dated Nov 2007. Its been 2 years almost. Any updates on this project? I’m curious, it is very interesting. Thanks for posting, and please post an update! (Couldn’t reach the webpage for digital opsis)

  • david

    Hi JC – the Digital Opsis works for me, try contacting Stelios.

    Cheers,

    David

  • JC

    David

    Yes the problem seems to be the Google Chrome browser. With firefox and IE, the page shows up fine. With chrome, all I get is a blank page.

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